The present invention relates to a device for driving a plain, or matrix liquid crystal display panel using STN liquid crystal and so on the like. More specifically, the present invention relates to a driving device suitable for Multiple Line Selection addressing. Further specifically, the present invention relates to a structure of a driving circuit suitable for half tone display by Pulse Width Modulation (PWM).
A plain matrix type liquid crystal display panel is composed of a liquid crystal layer interposed between a group of row electrodes and a group of column electrodes thereby providing pixels arranged in a matrix. Conventionally, such liquid crystal display panels are driven by a Voltage Averaging Method. In this method, the respective row electrodes are sequentially selected one by one, and data signals representative of the ON/OFF status of pixels are applied to the column electrodes in synchronization with each timing to be selected.
Consequently, each pixel receives a high voltage of one time slot (1/N of a frame time interval) within one frame period during which all of (N number of) the row electrodes are selected, while the same pixel receives a constant bias voltage in the remaining time interval ((N-1)/N of the frame time interval). When the liquid crystal material has a slow response, there can be obtained a brightness corresponding to an effective value of the applied voltage waveform during one frame period. However, if a frame frequency is lowered as the multiplexing number increases, a difference between one frame period and a liquid crystal response time is reduced, so that the liquid crystal responds to each applied pulse to thereby cause a brightness flicker called "frame response" which degrades the contrast.
Recently, "Multiple Line Selection" has been proposed as means to deal with such a problem of the frame response, for instance, as disclosed in Japanese Tokkai Hei 5-100642. In this Multiple Line Selection technique, each of the row electrodes is not selected one by one as was conventional, but a plurality of row electrodes are simultaneously selected to equivalently achieve the same effect as the high frequency drive, thereby preventing the above-mentioned frame response. As its different from the single line selection driving technique, multiple line selection requires a specific technique for realizing a free display. Namely, it is necessary to arithmetically process an original image data and supply the processed data to a column electrode. Practically, a plurality of row signals represented by a set of orthonormal functions are applied to the group of row electrodes in sequence of the set of orthonormal functions during each selecting period. On the other hand, a dot product computation is carried out sequentially between the set of orthonormal functions and a set of selected pixel data, and then a column signal that has a voltage level corresponding to a result of the computation is applied to the group of column electrodes in synchronization with the set sequential scanning during each selecting period.
The above-mentioned Multiple Line Selection driving technique can be also adapted to a half tone display. There are a variety of methods for half tone display, especially the Pulse Width Modulation technique, which can be easily combined with the Multiple Line Selection, for instance, as disclosed also in the above-mentioned Japanese Tokkai Hei 5-100642. In this method, a given pixel data has a plurality of bits and gray shading is displayed therewith. When the dot product computation is carried out between the set of orthonormal functions and the set of pixel data, the set of pixel data is divided by the bits to carry out the computation and generate column signal components corresponding to significance of the bits. Further, the column signal components are arranged in an order of bit significance during each selecting period to compose a column signal, which is applied to a group of column electrodes, thereby obtaining a desired half tone display.
FIG. 9 shows an example of column signal according to the PWM gray-scale technique. In this example, a pixel data is composed of 4 bits and can be displayed in 2.sup.4 =16 gray levels. Four column signal components A, B, C, and D are arranged in accordance with the significance of the respective bits during each of selecting periods .DELTA.t. A first column signal component A corresponds to a least significant bit, whose pulse width is represented by "1". A second column signal component B corresponds to a second least significant bit, whose pulse width is twice as large as that of the component A. A third column signal component C corresponds to a third least significant bit, whose pulse width is four times as large as that of the component A. A final column signal component D corresponds to a most significant bit, whose pulse width is eight times as large as that of the component A. Further, a voltage level of each column signal component is obtained by a dot product computation by the corresponding significance of each bit. An effective voltage during the selecting period .DELTA.t is obtained as a weighted mean value of the column signal components A to D. Further, the column signal component D corresponding to the most significant bit is the most dominant, while the column signal component A corresponding to the least significant bit makes the least contribution.
voltage levels of the column signal components A to D that are arranged as thus described are switched very swiftly during the selecting period .DELTA.t. Therefore, a waveform is distorted when the voltage level is switched, resulting in an error in the part hatched. As the difference between two adjacent voltage levels is increased, a degree of the distortion of the wavelength becomes larger. There is a problem that this error prevents accurate half-tone display. Especially, the error in column signal components corresponding to the more significant bits has more influence on fluctuation in half-tone display level compared with the error in those corresponding to the less significant bits. The example shown by FIG. 9 has a problem that the error in column signal components corresponding to the more significant bits is brought about according to voltage levels of the column signal components corresponding the less significant bits, resulting a large fluctuation finally.